RISC-V

TODO

Articles

• Гениальность микропроцессоров RISC-V

• Недостатки RISC-V

• RISC-V Bytes

• Изучаем RISC-V с нуля, часть 1: Ассемблер и соглашения

• High-Level Synthesis For RISC-V

• RISC-V с нуля

• Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip

• Linux in a Pixel Shader - A RISC-V Emulator for VRChat

• XiangShan open-source 64-bit RISC-V processor to rival Arm Cortex-A76

• RISC-V Adventures: Lightening

• Build a RISC-V CPU From Scratch

• Example RISC-V Assembly Programs

• What happens when you load into x0 on RISC-V?

• Designing a RISC-V CPU, Part 1: Learning hardware design as a software engineer

• RISC-V isn’t as interesting as you think

• The Genius of RISC-V Microprocessors

• Do Some ARM

• What Does RISC and CISC Mean in 2020?

• Getting Graphical Output from our Custom RISC-V Operating System in Rust

• Understanding Non-Local Jumps (setjmp/longjmp) in RISC-V Assembly

• Parsing RISC-V assembly

• RISC-V: What’s Missing And Who’s Competing

• Open-Source Hardware Momentum Builds

• RISC-V’s Expanding Footprint

• PicoRio Linux RISC-V SBC is an Open Source Alternative to Raspberry Pi Board

• RISC-V from scratch 1: Introduction, toolchain setup, and hello world!

• SiFive Core IP 20G1

• Will RISC-V Revolutionize Computing?

• Bare metal RISC-V programming in Go

• Learning embedded Rust by building RISC-V-powered robot - Part 1

• Sipeed MAiX RISC-V boards

• RISC-V Stumbling Blocks

• Процессор Snitch на базе RISC-V может похвастаться шестикратным приростом производительности

• RISC-V vs ARM

Courses / Videos

• RISC-V CPU In TypeScript

• RISC-V and the CPU Revolution, Yunsup Lee, Samsung Forum

• George Hotz | Programming | twitchcore: a little RISC-V core | in Python | in Verilog | on FPGA

• The Genius of the RISC-V Microprocessor - Erik Engheim - NDC TechTown 2021

• "Verified seL4 on secure RISC-V processors" - Gernot Heiser (LCA 2020)

Links

• RISC-V - Getting Started Guide

• opensbi - RISC-V Open Source Supervisor Binary Interface

• Building a RISC-V CPU Core

• RVVM - The RISC-V Virtual Machine

• RISC-V Instruction Set Manual

• RISC-V Assembly Programmer's Manual

• Awesome RISC-V